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EIA JESD 75-6:2006
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EIA JESD 75-6:2006
PSO-N/PQFN Pinouts Standardized for 14-, 16-, 20-, and 24-Lead Logic FunctionsThis standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices. The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
| Author | EIA |
|---|---|
| Editor | EIA |
| Document type | Standard |
| Format | File |
| ICS | 31.080.01 : Semiconductor devices in general
|
| Number of pages | 12 |
| Year | 2006 |
| Document history | |
| Country | USA |
| Keyword | EIA JESD 75;EIA 75;EIA 75.6;75;EIA JESD75-6 |
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