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ESD SP5.4.1:2017
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ESD SP5.4.1:2017
ESD Association Standard Practice for Latch-up Sensitivity Testing of CMOS/BiCMOS Integrated Circuits - Transient Latch-up Testing - Device LevelThis document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients.
| Author | ESD |
|---|---|
| Editor | ESD |
| Document type | Standard |
| Format | File |
| Confirmation date | 2018-02-27 |
| ICS | 17.220.20 : Measurement of electrical and magnetic quantities
|
| Year | 2018 |
| Document history | |
| Country | USA |
| Keyword | ANSI 5;ANSI/ESD SP 5;ANSI/ESD 5;5;ANSI/ESD SP5.4.1-2018 |
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